As the number of devices made on a single semiconductor substrate (silicon wafer) increases and the relative size of the devices decreases, problems both of performance and manufacturability arise. In the manufacture of MOSFETs, shallow (&lt;0.25 micron), low resistivity p-type source/drain (hereinafter S/D) regions in an n-type well are subject to low junction breakdown and high junction capacitance. Thus graded S/D regions have been suggested. These junctions have less abrupt changes in their doping profile across the junction, and higher breakdown voltage and lower junction capacitance. These graded junctions can be made by ion implanting a first implant (such as boron) at low energy and high dosage to give a pre-selected resistivity, followed by a second implant (also boron) at high energy and low dosage which sets the breakdown characteristics of the junction. These ion implant steps must be followed by an annealing step to redistribute the dopant and to heal any implant damage to the silicon crystal.
For example, Woo et al in U.S. Pat. No. 4,757,026 describes manufacture of MOSFETs having graded S/D junctions. According to the process described, two mask layers are deposited, and the second mask layer anisotropically etched to leave spacers of the second mask layer on sidewalls of an insulated gate electrode. A high dosage ion implant is carried out through the first mask layer and a high temperature anneal carried out to repair damage to the substrate. The spacers prevent ions from penetrating into the substrate adjacent the gate. The spacers are them removed and a second, low dosage ion implant is carried out, thereby implanting the substrate adjacent to the gate. A second anneal is then carried out.
A graded junction device of Woo et al is shown in FIG. 1 and comprises a high resistivity n-well 10; a thick field oxide region 11 overlying a portion of the n-well 10; a thin gate oxide layer 12 overlying a portion of the well 10 that forms the gate, and includes a channel region 13 in the substrate; a conductive gate layer 16 overlying the channel region 13 and the gate oxide layer 12; a low resistivity p-type S/D region 14 between the field oxide region 11 and the gate 16; and a high resistance p-type grading region 15 surrounding the S/D region 14 and separating it from the n-type well 10. Such a structure increases the breakdown voltage of a junction because of the separation of the heavily doped region and the n-type well; reduces the junction capacitance for the same reason; and reduces the effective gate length because of encroachment of the grading region under the gate oxide. However, a drive-in step is required between implant steps comprising heating at high temperatures for extended periods to activate and diffuse the ion implanted ions vertically into the silicon substrate. Another high temperature annealing step is required after the second ion implant to heal damage to the silicon substrate caused by the ion implantation. This crystal damage provides nucleation centers for the formation of dislocations and must be removed entirely.
However, as the width of various device components of transistors, including the S/D regions and gates, become smaller, the vertical depth of S/D regions must also be controlled, and the S/D regions are required to be shallower. Thus sub-micron CMOS manufacturing requires restriction to low temperature manufacturing because of the need to decrease vertical dopant diffusion to achieve very shallow S/D junctions and channel profiles.
In order to obtain shallow junctions, the processing temperatures must be limited to obtain control of the dopant diffusion vertically into the bulk silicon, while allowing some lateral diffusion of the dopants to ensure some overlap of the gate/channel regions and S/D junctions, thereby ensuring continuity between these regions. This continuity is required for current drive capability and "hot electron" stability.
Since in general the diffusion coefficients vertically and laterally are about the same, this is a difficult maneuver.
Thus there are two competing manufacturing requirements; high temperature annealing is required to remove crystal damage to the silicon wafer, and low temperatures are required to obtain shallow S/D regions.
Ion implantation damage to a silicon crystal can be avoided by ion implanting through a polysilicon or doped silicide buffer layer. The ion implant damage is thus confined to the buffer layer, and does not damage the silicon crystal at all. Thus formation of dislocations and consequent junction leakage current will be reduced using ion implantation through a buffer layer. However, in the absence of a thermal heating step, the diffusion depth of the junction is insufficient, and thus good junction characteristics cannot be obtained. Further, insufficient out-diffusion from the polysilicon or silicide layer may cause more junction leakage via silicide spiking or tunneling. The out-diffusion of dopants under polysilicon is limited in the absence of high temperatures, and the presence of oxide residues at the polysilicon-silicon interface may block out-diffusion entirely, thereby degrading the junction characteristics. Incomplete out-diffusion also affects the lateral junction as well.
Thus improved shallow junction MOSFETs and method of manufacturing them which avoids high temperature processing has been sought.